The application of flash memory as mass data storage has placed additional demands on the cost-per-bit of flash memories and the required total memory density in systems. Traditional NVMs, denoted as Single Level Cell (SLC), have a one-to-one relationship between memory density and number of memory cells. To meet the higher memory capacity required of today's flash memory and to reduce per bit cost, Multi-Level Cell (MLC) NVMs been proposed. Flash memories with two (2) bits per cell have been in production (M. Bauer et. al. and Tae-Sung Jung et. al.) for some time. For an n-bit per cell NVM, the number of threshold voltage levels associated with the voltages stored in the cell is given by 2n. For example, for two (2) bits per cell NVM, which can represent any one of four different values, the number of threshold voltage levels associated with the voltage stored in the cell is four (4). For a four (4) bit per cell NVM, where each cell can store any one of sixteen different values, the number of threshold voltage levels becomes sixteen (16), and so forth. Increasing the number of bits stored in a single NVM cell exponentially increases the required number of threshold voltage levels. This imposes a very challenging limitation on MLC NVM. The number of resolvable threshold voltage levels within a limited threshold voltage range of NVM cells becomes an important key issue for the improvement of the bit capacity per NVM cell.
In conventional MLC NVM, the threshold voltage levels of NVM cells are defined and stored in reference cells. The reference NVM cells are pre-programmed to defined threshold voltage levels. The bits stored in an NVM cells as an analog voltage level are then read out by comparing the responding current or voltage from the cell when turned on by the appropriate gate voltage with a current or voltage in a reference cell under the same biasing condition. Due to the non-uniformity of programming conditions and variations in the fabrication process used to fabricate NVM cells, the distribution of the actual threshold voltage level associated with a given value stored in cells of an NVM array hinders increasing the number of resolvable threshold voltage levels. Other factors such as the sense amplifier DC offset and changes in NVM devices with use compared with the less used reference devices also contribute to this limitation in the number of different values that can be stored in an NVM MLC.
To improve the programming accuracy for NVM threshold voltage levels, a verification circuit to verify the threshold voltages of programmed NVM cells is usually included. Comparing the responding current or voltage of a programmed NVM MLC with that of a reference cell pre-programmed to a threshold voltage level under the same biasing condition is the conventional verification scheme. However, the conventional scheme is also affected by the non-uniformity of the reference and memory cells and their write/erase history.